Conformal thin films over textured capacitor electrodes

ABSTRACT

Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a continuation of U.S. patentapplication Ser. No. 09/791,072, filed on Feb. 22, 2001, which is adivisional of U.S. patent application Ser. No. 09/452,844, filed on Dec.3, 1999.

FIELD OF THE INVENTION

[0002] The invention relates generally to forming thin films overtextured bottom electrodes, and more particularly to providing highpermittivity dielectric and top electrode materials with near perfectconformality over memory cell bottom electrodes including hemisphericalgrain (HSG) silicon.

BACKGROUND OF THE INVENTION

[0003] When fabricating integrated circuits, layers of insulating,conducting and semiconducting materials are deposited and patterned,layer by layer, to build up the desired circuit. Many types of circuitsincorporate capacitors, each of which include a dielectric layersandwiched two plates or electrodes. Memory chips such as dynamic randomaccess memories (DRAMs), in particular, employ capacitors to storecharge in memory cells. Each memory cell can represent one bit of data,where the capacitor can either be charged or discharged to representlogical states.

[0004] In accordance with the general trend in the semiconductorindustry, integrated circuits are continually being scaled down inpursuit of faster processing speeds and lower power consumption. As thepacking density of memory chips continues to increase, each capacitor inthe more crowded memory cell must still maintain a certain minimumcharge storage to ensure reliable operation of the memory cell withoutexcessive refresh cycling. It is thus important that, with progressivegenerations of circuit design, capacitor designs achieve ever higherstored charge for the shrinking area of the chip (or footprint) allottedto each cell. Techniques have therefore been developed to increase thetotal charge capacity of the cell capacitor for a given footprintallotment.

[0005] The amount of charge stored on the capacitor is proportional tothe capacitance, C=kk₀A/d, where k is the permittivity or dielectricconstant of the capacitor dielectric between two electrodes; k₀ is thevacuum permittivity; A is the electrode surface area; and d is thespacing between the electrodes, also representing the thickness of theinter-electrode dielectric. Early techniques have focused on increasingthe effective surface area of the electrodes by creating foldingstructures for stacked capacitors or trench capacitors. Trenchcapacitors are formed within the semiconductor substrate in which thetransistors are generally formed, whereas stacked capacitors are formedabove the transistors. Such structures better utilize the available chiparea by creating three-dimensional shapes to which the conductiveelectrodes and capacitor dielectric conform.

[0006]FIG. 1A illustrates a memory cell 10 incorporating an exemplarystacked capacitor above a semiconductor substrate 12. The illustratedcapacitor design is known in the industry as a “stud” capacitor.Transistors are first formed, including gate stacks 14 formed over thesubstrate 12 and heavily doped active areas 16 within the substrate 12.A contact 18 reaches through an insulating layer 20 that overlies thetransistors. This contact 18 electrically connects a lower or storageelectrode 22, of the capacitor 11, which is formed over the insulatinglayer 20. The stud shape presents a larger surface area for the lowerelectrode 22, relative to the footprint of the substrate over which itis formed. A thin capacitor dielectric layer 24 coats the lower orbottom electrode 22, and an upper or top electrode 26 is formed over thecapacitor dielectric 24.

[0007]FIG. 1B, for example, illustrates a memory cell 10 a with adifferent stacked capacitor design, where like parts are referred to bylike reference numerals. As in FIG. 1B, a capacitor 11 a is shown over asubstrate 12, including transistors covered with an insulating layer 20.The capacitor 11 a, however, conforms to a generally cylindrical shape.In particular, a lower or bottom electrode 22 a, electrically connectingto an underlying transistor by the contact 18, conforms to a cylinder,presenting a larger surface area relative to the footprint of thesubstrate over which it is formed. With both inner and outer surfacesexposed, as shown, the bottom electrode 22 a has an even largereffective surface area than the corresponding bottom electrode 22 of thestud capacitor 11 in FIG. 1A. A thin capacitor dielectric layer 24 acoats the bottom electrode 22 a, and a top electrode 26 a is formed overthe capacitor dielectric 24 a. “Crown” structures are similar to theillustrated cylindrical capacitor 11 a of FIG. 1B but further includemultiple concentric cylinders. Other stacked capacitor designs resemblemushroom shapes, finned structures, pins and a variety of othercomplicated structures formed above a semiconductor substrate.

[0008]FIG. 2, in contrast to the stacked capacitors of FIGS. 1A and 1B,illustrates a memory cell 30 incorporating an exemplary trench capacitor31, formed largely within a semiconductor substrate 32. As with thestacked capacitors of the previous figures, a transistor includes a gatestack 34 over the substrate 32 and heavily doped active areas 36 withinthe substrate 32. The drain region (one of the active areas 36)electrically contacts a lower or storage electrode 42 of the capacitor31. Doping or otherwise making conductive the walls of a trench in thesemiconductor substrate 32 forms this lower electrode 42. By conformingto the walls of the trench, a larger surface area is provided for thelower electrode 42, relative to the footprint of the substrate 32 inwhich it is formed. A thin capacitor dielectric layer 44 coats thebottom electrode 42, and a top or reference electrode 46 is formed overthe capacitor dielectric 44.

[0009] Relying solely on such structures for increasing the capacitanceof the memory cell, however, becomes impractical with advancinggenerations of memory chip circuit designs. The surface area of a studcapacitor can theoretically be increased infinitely simply by increasingthe height of the bottom electrode. Similarly, the depth of trenchcapacitors can be increased almost to the thickness of the substratewithin which it is formed. Unfortunately, limits are imposed upon theheight or depth of features in integrated circuits. As is well known inthe art, it can be difficult to conformally coat, line or fill featureswith high steps using conventional deposition techniques. Additionally,increased topography on a chip can adversely affect the resolution oflater photolithographic processes.

[0010] Rather than relying solely upon the height or depth of the cellcapacitor, therefore, a microstructure can be added to further increasethe surface area of the capacitor electrodes, by providing a textured orroughened surface to the macrostructural folds of the lower electrode.For example, polycrystalline conductive materials can be roughened bypreferentially etching along grain boundaries, as disclosed, forexample, in U.S. Pat. No. 3,405,801, issued to Han et al. Alternatively,U.S. Pat. No. 5,372,962, issued to Hirota et al., describes variousselective etch processes for perforating a polysilicon layer.

[0011] Another class of electrode texturing techniques involvesformation of hemispherical grained (HSG) silicon. Several methods forforming HSG silicon are known, including direct deposition, wherebydeposited polysilicon selectively grows over nucleation sites, andredistribution anneal of amorphous silicon, whereby thermal energycauses silicon atoms to migrate about a surface and conglomerate aboutnucleation sites. FIGS. 1A and 1B show the lower electrodes 22, 22 aincluding HSG silicon microstructures 28, 28 a formed over the basicstud or cylinder configurations, thereby increasing the effectiveelectrode surface area. Similarly, the bottom electrode 42 of FIG. 2includes an HSG silicon layer 48 over the basic trench configuration,further increasing the electrode surface area.

[0012] In order to fully realize the advantage of the increased surfacearea of textured bottom electrodes, the capacitor dielectric layershould conform closely to the surface of the bottom electrode. While thedielectric thickness (“d” of the capacitance formula set forth above)should be minimized in order to maximize capacitance, too thin acapacitor dielectric risks leakage current across the capacitorelectrodes. Leakage current may result from pinholes in the dielectricand quantum tunneling effects, both of which phenomena are more likelyto occur with thinner dielectrics. Thin capacitor dielectric layers arethus characterized by a low breakdown voltage, limiting the charge thatmay be stored on the bottom electrode before breakdown leakage occurs.Accordingly, capacitor dielectric layers may be characterized by acertain minimal thickness necessary to avoid breakdown, depending uponthe selected dielectric material.

[0013] Referring to FIG. 3, an enlarged view of an HSG silicon layer 50is illustrated. The layer 50 comprises hemispherical grains 52 ofconductively doped polycrystalline silicon (polysilicon, or simply poly)over a conductive substrate 54. The grains 52 have grain sizes rangingfrom about 50 Å to about 750 Å. A dielectric layer 56, deposited by CVD,is shown over the HSG layer 50. The illustrated dielectric comprisesconventional dielectric materials, such as silicon oxide (SiO₂) and/orsilicon nitride (Si₃N₄), which are well-understood and easily integratedwith conventional fabrication process flows. CVD processes for thesematerials, for example, are well developed.

[0014] As shown, the dielectric layer 56 deposited by CVD is relativelyconformal over the surfaces of the HSG silicon layer 50. However,conventional CVD processes cannot produce perfectly conformaldielectrics over high surface area textures, such as HSG silicon, due toa variety of factors. CVD inherently results in disparate depositionrates at different points of the topography across the workpiece.Non-uniformities in temperature across a workpiece, particularly acrosslarge workpieces like 300-mm wafers, can strongly influence thicknessuniformity of a CVD layer. Variations in reactant concentration, due toreactor design, gas flow dynamics and the depletion effect, similarlyaffect the thickness uniformity across large workpieces. Due to theseand other problems, growth rates and conformality cannot be controlledwith absolute precision using conventional CVD.

[0015] Independently of variations across the workpiece, non-uniformityalso results on a microlevel over rugged surfaces. In particular, at theneck region 60 between adjacent grains 52 that approach or intersectwith one another, the dielectric layer bridges the adjacent grains 52and produces an effectively greater dielectric thickness than over thetop surfaces 61 of the grains. In some cases, reentrant profiles 62 areproduced between blossoming or mushroom-shaped grains 52. CVD of adielectric over the neck regions 60 of such structures results in eithercompletely filling the neck region between grains 52 or leaving voids 64between the grains 52 while the dielectric pinches off. In either case,the top electrode cannot conform to the surfaces of the grains 52, suchthat the lower portions of the grains 52 are effectively lost and do notcontribute to capacitance.

[0016] If the dielectric 56 is deposited to the minimal thickness inneck regions 60 between HSG silicon grains, the dielectric over the topsurfaces is too thin and can lead to leakage and consequent data errors.Accordingly, the dielectric 56 must be deposited to the minimalthickness required to avoid leakage over top surfaces 61 of the grains52. The dielectric 56 at the neck regions 60 the grains 52 is thusthicker than theoretically necessary, leading to reduced capacitance.From another perspective, dielectric bridging across the neck regions 60results in effective loss of surface area from lower portions of the HSGgrains 52, such that the full advantage of HSG silicon is not realized.

[0017] Due in part to such limitations on capacitance enhancement byincreasing electrode surface area, more recent attention has beenfocused instead upon methods of increasing the dielectric constant (k)of the capacitor dielectric. Much effort has been aimed at integratingnew dielectric materials having higher k values. High k materialsinclude aluminum oxide (Al₂O₃), tantalum oxide (Ta₂O₅), barium strontiumtitanate (BST), strontium titanate (ST), barium titanate (BT), leadzirconium titanate (PZT), and strontium bismuth tantalate (SBT). Thesematerials are characterized by effective dielectric constantssignificantly higher than conventional dielectrics (e.g., silicon oxidesand nitrides). Whereas k equals 3.9 for silicon dioxide, the dielectricconstants of these new materials can range from on the order of 10(aluminum oxide) to 300 (BST), and some even higher (600 to 800). Usingsuch materials enables much greater increases in cellcapacitance/footprint.

[0018] Moreover, dramatic increases in k value for the capacitordielectric allow use of smaller and simpler capacitor designs for agiven stored charge requirement. Reducing the surface area needs for acell capacitor can simplify the integration process and allow greaterpacking densities for future circuit designs.

[0019] Integrating high k materials into conventional process flows,however, has proven challenging. Some materials, such as Ta₂O₅, BST andother “exotic” materials, tend to involve highly oxidizing, hightemperature deposition and post-deposition anneal conditions, leading tooxidation of traditional electrode materials and even diffusion ofoxygen into lower circuit elements. Other materials, such as ZrO₂ andTiO₂, have highly inconsistent properties, depending upon a variety ofprocessing conditions.

[0020] Accordingly, a need exists for more effective methods ofincreasing the storage capacitance for integrated memory cells.

SUMMARY OF THE INVENTION

[0021] In satisfaction of this need, methods are provided herein fordepositing dielectric and top electrode materials over textured bottomelectrode surfaces. Advantageously, the methods attain highconformality, such that only the minimum required thickness of thelining layer need be formed on all surfaces. The methods enabledeposition of high dielectric constant (high k) materials overhemispherical grain (HSG) silicon under conditions favorable tomaintaining silicon electrodes.

[0022] In general, the methods comprise cycles of alternating reactantphases, wherein each phase has a self-limiting effect. Metal oxides andternary materials having dielectric constants of greater than about 10can be formed by alternately adsorbing self-terminated metal or siliconcomplex monolayers through ligand-exchange reactions. The ligandspresent on the adsorbed metal or silicon complex are then removed bypresence of an oxygen-containing species, leaving OH groups and oxygenbridges for halide or organic monolayers. Examples are provided hereinfor simple binary metal oxides, ternary materials such as metalsilicates and nanolaminates comprising alternating ultrathin dielectriclayers of different compositions.

[0023] Advantageously, the methods enable forming uniformly thickdielectric layers over HSG silicon, desirably as thin as possiblewithout inducing leakage current through the capacitor dielectric soformed. Moreover, the methods facilitate a combination of high kmaterials with high surface area, textured electrodes. Capacitance isthus maximized, facilitating further scaling of critical dimensionswithout loss of cell reliability.

[0024] Similar alternating chemistries are preferably employed to formtop electrode materials over the conformal dielectric layers. Examplesare provided herein for metal nitride barriers as well as elementalmetal layers. Following formation of thin, conformal conductive layer(s)by the preferred methods, conventional deposition with reducedconformality can complete the desired thickness of the top electrodewithout sacrificing capacitance. Conformal capacitor dielectric and topelectrodes formed by the preferred methods thus enable taking fulladvantage of the increased surface area afforded by textured bottomelectrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] These and other aspects of the invention will be readily apparentto the skilled artisan in view of the description below, the appendedclaims, and from the drawings, which are intended to illustrate and notto limit the invention, and wherein:

[0026]FIG. 1A is a schematic cross-section of an integrated stacked(stud) capacitor memory cell incorporating hemispherical grain (HSG)silicon;

[0027]FIG. 1B is a schematic cross-section of another integrated stacked(cylindrical) capacitor memory cell incorporating HSG silicon;

[0028]FIG. 2 is a schematic cross-section of an integrated trenchcapacitor memory cell incorporating HSG silicon;

[0029]FIG. 3 is an enlarged view of a portion of a capacitorincorporating HSG with a dielectric formed by conventional chemicalvapor deposition (CVD);

[0030]FIG. 4A is a flow chart generally illustrating a method of formingmemory cells with conformal dielectric layers over HSG silicon;

[0031]FIG. 4B is a flow chart more particularly illustrating a method offorming memory cells with conformal ternary dielectric materials overHSG silicon;

[0032]FIG. 5 is an exemplary gas flow diagram for depositing binarydielectric layers, in accordance with preferred embodiments of thepresent invention;

[0033]FIG. 6 is an exemplary gas flow diagram for depositing a ternarydielectric layer, in accordance with another preferred embodiment;

[0034]FIG. 7 is a partial, schematic cross-section of a memory cellcapacitor, including a conformal ultrathin dielectric over HSG silicon;

[0035]FIG. 8 is a partial, schematic cross-section of a partiallyfabricated memory cell capacitor, including a conformal ultrathindielectric over a barrier layer and HSG silicon;

[0036]FIG. 9 is a partial, schematic cross-section of a partiallyfabricated memory cell capacitor, including a nanolaminate dielectricover HSG silicon; and

[0037]FIG. 10 is a partial, schematic cross-section of a memory cellcapacitor with an HSG silicon bottom electrode, including both aconformal ultrathin dielectric and a conformal barrier layer thereover.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0038] Though described in the context of certain preferred materials,it will be understood, in view of the disclosure herein, that thedescribed methods and structures will have application to a variety ofother materials suitable for capacitor dielectrics over rugged surfaces.Moreover, while illustrated for memory cell storage capacitors, theskilled artisan will readily appreciate application of the describedmethods to other roughened electrodes, such as the floating gateelectrode of an Electrically Erasable Programmable Read Only Memory(EEPROM) device.

[0039] As discussed in the Background section above, coating capacitorelectrodes, and particularly electrode structures bearing hemisphericalgrain (HSG) silicon, by conventional chemical vapor deposition (CVD)produces less than perfect conformality. While much research has beendevoted to obtaining more conformal step coverage of semiconductorstepped features in general, it is very difficult to supply the sameconcentration of depositing species to all surfaces of such structures.In particular, it is difficult to supply the same concentration ofdepositing species at the upper surfaces of HSG grains as supplied toneck regions between grains. This problem is particularly exacerbatedwhere the textured electrode conforms to a three-dimensional foldingstructure, such as the stacked and trench designs of FIGS. 1A to 2, andeven more so for structures with interior volumes like that of FIG. 1B.Accordingly, full advantage of the increased surface area of the HSGsilicon is not realized.

[0040] By providing almost perfect step coverage, the preferredembodiments advantageously obtain the minimum necessary thickness forthe desired capacitor dielectric layers over all surfaces of HSG grains.Desirably, the methods of the preferred embodiment are less dependentupon the relative concentration of reactant species over grains ascompared to confined grain intersections.

[0041] Moreover, the preferred embodiments provide methods of depositinghigh k materials in a manner that enables integration with high-surfacearea textured surfaces and with silicon electrodes, which is most oftenemployed to produce microstructural roughness such as an HSG morphology.Rather than presenting a choice between high surface area textures overthree-dimensional folding structures and high k dielectrics, thepreferred embodiments allow the use of both techniques to achieve veryhigh capacitance/footprint in a repeatable, production-worthy process.

[0042] The preferred embodiments provide exemplary processes fordepositing Al₂O₃ (k˜10), ZrO₂ (k˜12-20), TiO₂ (k˜20-50), mixed zirconiumsilicon oxide (k˜8-13), and nanolaminate dielectrics formed bycombinations of the above. Similarly, methods are provided fordepositing electrode materials over the dielectric and HSG silicon.These materials are all formed by methods compatible with HSG silicon,furthermore producing almost perfect conformality. Thus, the preferredembodiments allow increased capacitance not only due to the high kdielectric materials, but also due to taking full advantage of theincreased surface area afforded by HSG silicon. Such conformalityobtains even over high aspect ratio structures like stacked and trenchcapacitor designs.

[0043] Further advantages of the preferred processes will be apparentfrom the discussion below.

[0044] Methods of Forming Conformal Capacitor Dielectrics

[0045]FIG. 4A generally illustrates a method of forming capacitordielectric layers with high step coverage. The preferred method is aform of atomic layer deposition (ALD), whereby reactants are supplied tothe workpiece in alternating pulses in a cycle. Preferably, each cycleforms no more than about one monolayer of material by adsorption andmore preferably by chemisorption. The substrate temperature is keptwithin a window facilitating chemisorption. In particular, the substratetemperature is maintained at a temperature low enough to maintain intactbonds between adsorbed complex and the underlying surface, and toprevent decomposition of the precursors. On the other hand, thesubstrate temperature is maintained at a high enough level to avoidcondensation of reactants and to provide the activation energy for thedesired surface reactions in each phase. Of course, the appropriatetemperature window for any given ALD reaction will depend upon thesurface termination and reactant species involved.

[0046] Each pulse or phase of each cycle is preferably self-limiting ineffect. In the examples set forth below, each of the phases areself-terminating (i.e., an adsorbed and preferably chemisorbed monolayeris left with a surface non-reactive with the chemistry of that phase).An excess of reactant precursors is supplied in each phase to saturatethe structure surfaces. Surface saturation ensures reactant occupationof all available reactive sites (subject to physical size restraints, asdiscussed in more detail below), while self-termination prevents excessfilm growth at locations subject to longer exposure to the reactants.Systematic utilization of saturation through chemisorption, i.e.,self-terminating chemistries, ensure excellent step coverage.

[0047] Prior to forming the dielectric layer, an integrated circuit isfirst partially fabricated to the point of constructing a capacitorlower or bottom electrode. Typically, the bottom electrode serves as astorage electrode in the memory cell. For purposes of the presentdescription, however, the bottom electrode represents the first-formedcapacitor electrode or plate, regardless of whether it serves as thestorage or reference plate in the completed integrated circuit.

[0048] As illustrated in FIG. 4A, the process in accordance withpreferred binary material embodiments begins with formation 100 of abottom electrode structure in an integrated circuit. The basic bottomelectrode structure can be planar, such as the floating gate in anEEPROM device. Preferably, however, the bottom electrode conforms to athree-dimensional folding structure having a greater surface area thanthe substrate footprint occupied by the memory cell. More preferably,the capacitor bottom electrode takes the form of a stacked capacitor,such as the stud configuration illustrated in FIG. 1A or the cylindricalconfiguration illustrated in FIG. 1B. The skilled artisan will readilyappreciate that the methods disclosed herein are also applicable toother stacked capacitor designs, such as crowns, finned structures,combs, pins, etc. In another arrangement, the capacitor bottom electrodeis formed by conductively doping and/or conductively lining the walls ofa trench formed within a semiconductor substrate, as illustrated in FIG.2.

[0049] After formation of the bottom electrode macrostructure, in eithera stacked or trench arrangement, the bottom electrode is then provided101 with a textured or roughened microstructure superimposed upon thethree dimensional folding shape, further enhancing the surface area ofthe bottom electrode, preferably in the form of a layer of HSG silicon.

[0050] In an exemplary fabrication, conducted in a batch system soldunder the trade name A600 UHV™ by ASM, International, Inc, the HSGsilicon is formed by amorphous silicon deposition, seeding andredistribution anneal. A three-dimensional folding structure is formedof or coated with amorphous silicon. While in some processes, theamorphous silicon deposition can be conducted in situ within the samereaction chamber as the subsequent steps, in the illustrated embodiment,the folding amorphous silicon structure is formed prior transferringwafers to the A600 UHV™ system.

[0051] Within the preferred reactor, the amorphous silicon surface isseeded. In the illustrated embodiment, the temperature is raised to alevel within the range of about 550° C. to 575° C. (e.g., about 560° C.)while the reactor pressure is preferably reduced to on the order ofabout 10⁻⁵ Torr. A seeding gas in the preferred embodiment ismonosilane, provided with a silane partial pressure of about 4×10⁻⁶Torr. After seeding, the density of which can be varied according todesign, continued thermal treatment at the desired temperature resultsin a redistribution of mobile amorphous silicon. Silicon atoms tend toagglomerate about the seed or nucleation sites formed by the silane. Theentire process takes on the order of about 10 minutes and 120 minutesfor the batch system, including temperature ramp, seeding and anneal.The skilled artisan will readily appreciate numerous other techniquesfor forming HSG silicon.

[0052] The HSG grains produced by the preferred process can range insize from about 50 Å to 750 Å, with more a typical range of about 300 Åto 500 Å. The process conditions affecting nucleation density and HSGsilicon grain size are typically selected to leave grains largelyseparated from one another. Such an arrangement maximizes electrodesurface area within the constraint of allowing most of the subsequentdielectric and top electrode layers to fit between the grains. As willbe appreciated from the enlarged views of FIGS. 7 through 10, however,the grains randomly converge at some locations due to the inherentlyrandom seeding process. Moreover, the preferred dielectric and topelectrode layers enable use of denser, less separated grains, thusincreasing the usable surface area.

[0053] As will be appreciated by the skilled artisan, the bottomelectrode preferably serves as the storage node of a memory cell in adynamic random access memory (DRAM) array. After fabrication, the bottomelectrode is typically isolated from the bottom electrodes of othercells across the array, as shown in FIGS. 1A, 1B and 2.

[0054] The bottom electrode structure so formed is thereafter coatedwith high step coverage. In accordance with the preferred embodiments,the dielectric layer is formed by a periodic process in which each cycleforms no more than about one monolayer of dielectric material upon theworkpiece in a self-limiting manner. Preferably, each cycle comprises atleast two distinct phases, wherein each phase is a saturative reaction,i.e., self-limitingly, leaving no more than about one atomic monolayerof the desired dielectric material.

[0055] If necessary, the exposed surfaces of the bottom electrode (e.g.,the HSG silicon of the preferred embodiments) are terminated 102 toreact with the first phase of the ALD process. The first phases of thepreferred metal oxide embodiments (see Tables I to V) are reactive, forexample, with hydroxyl (OH) or ammonia (NH₃) termination. In theexamples discussed below, silicon surfaces of HSG silicon will notgenerally require a separate termination. Exposure to a clean roomenvironment results in native oxide formation that naturally provides OHtermination 102. Where HSG is formed in situ or in a cluster tool priorto dielectric formation, it may be desirable to expose the HSG to H₂Ovapor, for example, as a surface preparation or termination 102treatment. In other arrangements (see the discussion of Tables II andIII below and FIG. 8), metal oxides can also be formed directly onsilicon nitride without a separate termination step. In other words,nitridation of HSG silicon can serve as the termination 102.

[0056] After initial surface termination 102, if necessary, a firstchemistry is then supplied 104 to the workpiece. In accordance with thepreferred metal oxide embodiments, discussed in more detail below withrespect to FIG. 5, the first chemistry comprises a metal-containingcompound that is reactive with the terminated surfaces left by theprevious step 102. Accordingly, a metal complex replaces the surfacetermination by means of ligand exchange. The resultant metal-containingmonolayer is desirably self-terminating, such that any excessconstituents of the first chemistry do not further react with themonolayer formed by this process. Preferably a halide or organic ligandterminates the metal-containing monolayer.

[0057] The metal-containing reactive species is preferably supplied ingaseous form, and is accordingly referred to hereinbelow as a metalsource gas. The first chemistry is then removed 106 from the reactionchamber. In the illustrated embodiments, step 106 merely entailsstopping the flow of the first chemistry while continuing to flow acarrier gas for a sufficient time to diffuse or purge excess reactantsand reactant by-products out of the reaction chamber, preferably withgreater than about two reaction chamber volumes of the purge gas, morepreferably with greater than about three chamber volumes. In theillustrated embodiment, the removal 106 comprises continuing to flowpurge gas for between about 0.1 seconds and 20 seconds after stoppingthe flow of the first chemistry. Inter-pulse purging is described inco-pending U.S. patent application having Ser. No. 09/392,371, filedSep. 8, 1999 and entitled IMPROVED APPARATUS AND METHOD FOR GROWTH OF ATHIN FILM, the disclosure of which is incorporated herein by reference.In other arrangements, the chamber may be completely evacuated betweenalternating chemistries. See, for example, PCT publication number WO96/17107, published Jun. 6, 1996, entitled METHOD AND APPARATUS FORGROWING THIN FILMS, the disclosure of which is incorporated herein byreference. Together, the adsorption 104 and removal 106 of excessreactant and by-products represent a first phase in an ALD cycle.

[0058] When the unreacted (or excess) reactants of the first chemistryhave been removed 106 from the chamber, a second chemistry is supplied108 to the workpiece. The second chemistry desirably reacts with theself-terminated monolayer formed in step 104. In the illustrated metaloxide embodiments, described in more detail below with respect to FIG.5, this reaction comprises supplying an oxygen source gas to theworkpiece. Oxygen or an oxygen-containing complex from the oxygen sourcegas preferably reacts with upon the previously adsorbed metal complex toleave a metal oxide monolayer in place of the metal complex monolayer.

[0059] In other arrangements, the second chemistry may simply remove theligand termination of the adsorbed metal complex monolayer formed instep 104 (e.g., by sublimation or reduction) or otherwise prepare themonolayer for oxidation or chemisorption of a further chemistry.

[0060] Desirably, the reaction 108 is also self-limiting. Reactantssaturate the limited number of reaction sites left by step 104.Temperature and pressure conditions are preferably arranged to avoiddiffusion of reactants from the second chemistry through the monolayerto underlying materials. The second chemistry also leaves a surfacetermination that is not reactive with excess reactants in the secondchemistry, thus operating to limit the deposition in a saturativereaction phase. In the illustrated embodiments of Tables I to V below,hydroxyl (OH) tails and oxygen bridge termination on a metal oxidemonolayer are non-reactive with excess oxygen source gases of the secondchemistry.

[0061] After a time period sufficient to completely saturate the surfaceof the metal-complex monolayer through chemisorption (or self-limitingreaction) of the second chemistry, the excess second chemistry isremoved 110 from the workpiece. As with the removal 106 of the firstchemistry, this step 110 preferably comprises stopping the flow of thesecond chemistry and continuing to flow carrier gas for a time periodsufficient to purge excess reactants and reaction by-products of thesecond chemistry from the reaction chamber. For example, reactants andreaction by-products can be removed by flowing purge gas after stoppingthe flow of the first chemistry, preferably with at least about twochamber volumes of purge gas and more preferably with at least aboutthree chamber volumes. In the illustrated embodiment, the removal 110comprises continuing to flow purge gas for between about 0.1 seconds and20 seconds after stopping the flow of the first chemistry. Together, thereaction 108 and removal 110 represent a second phase 111 in an ALDcycle.

[0062] In the illustrated embodiment, where two phases are alternatedonce the excess reactants and by-products of the second chemistry havebeen purged from the reaction chamber, the first phase of the ALDprocess is repeated. Accordingly, supplying 104 the first chemistryagain to the workpiece forms another self-terminating monolayer.

[0063] The two phases 107, 111 thus represent a cycle 115 repeated toform monolayers in an ALD process. The first chemistry generally reacts(in a ligand-exchange) with or chemisorbs upon the termination left bythe second chemistry in the previous cycle. If necessary, the cycle 115can be extended to include a distinct surface preparation, similar tostep 102, as shown in dotted lines in FIG. 4. The cycle 115 thencontinues through steps 104 to 110. This cycle 115 is repeated asufficient number of times to produce a dielectric layer over the HSGsilicon of a thickness sufficient to avoid current leakage duringcircuit operation. Alternatively, a thinner layer can be followed byfurther dielectric layers, deposited by a similar ALD process, to form astack of dielectric sublayers, as will be better understood from thediscussion of FIG. 9 below.

[0064] With reference to FIG. 4B, additional chemistries can also beincluded in each cycle. In FIG. 4B, steps corresponding to those of FIG.4A are referenced by numerals with the same last two digits in a 200series, rather than the 100 series of FIG. 4A. Accordingly, steps200-210 are similar to corresponding steps 100-110 of FIG. 4A.

[0065] The illustrated cycle 215 of FIG. 4B, however, extends to includetwo additional phases. The first phase 207 and second phase 211 form aself-terminated metal oxide or silicon oxide monolayer. A third phase219 and fourth phase 223 form another self-terminated metal oxide orsilicon oxide monolayer. Note that the composition of the secondmonolayer preferably differs from the composition of the first monolayerat the discretion of the recipe designer. See, e.g., the metal silicateexample of Table VI below.

[0066] In particular, after a first metal/silicon phase 207 and firstoxygen phase 211 form a first metal oxide or silicon oxide monolayer, asecond metal or silicon source gas is supplied 216 to form aself-limiting or self-terminating metal or silicon complex monolayerover the previously formed metal/silicon oxide. Similar to the firstmetal/silicon phase 207, the metal/silicon gas source can react byligand-exchange (chemisorption) upon the previously formed metal/siliconoxide. Following another removal 218 (by evacuation or preferably bypurging) of the reactants, a second oxygen gas source is supplied 220and then removed 222. The second oxygen step 220 (or oxygen phase 223)is also self-limiting. As with the first oxygen step 208, the oxygen gassource can react by ligand-exchange (chemisorption).

[0067] Though the illustrated process includes four phases in each cycle215, the cycle 215 will be referred to herein as a “ternary cycle 215,”since it produces a ternary dielectric. This is due to the fact that thesecond phase 211 and fourth phase 223 both contribute the same element(oxygen) to the growing dielectric layer. Note that, in otherarrangement, depending upon the desired oxygen content in the dielectriclayer, either the second phase or the fourth phase can be omitted. Insuch a case, consecutive chemistries would be selected to effectligand-exchange reactions to produce surface termination with smallenough ligands to permit some diffusion of a subsequent chemistry,and/or to have intermediate reduction phases in place of the omittedoxygen phase.

[0068] The second metal/silicon source gas in the third phase 219 can bea metal halide or metallorganic precursor, producing a metal complexmonolayer self-terminated with halide or organic ligands that arenon-reactive with the second metal/silicon source gas. In the example ofTable VI, however, the second metal/silicon source gas comprises asilicon source gas conducive to self-limiting chemisorption, such as3-aminopropyltriethoxysilane (NH₂CH₂CH₂CH₂—Si(O—CH₂CH₃)₃ or AMTES) or3-aminopropyltrimethoxsilane (NH₂CH₂CH₂CH₂—Si(O—CH₃)₃ or AMTMS)compound, or a halosilane. Note that the sequence of the metal sourceand silicon source phases can be reversed.

[0069] The oxygen source gas of the fourth phase 220 can be the same ordiffer from that of the second phase 211. The inventors have foundcertain oxidants (e.g., ozone) to be advantageous for oxidizing metal orsilicon complex monolayers having organic ligands, whereas otheroxidants (e.g., water) are more advantageous for halide-terminated metalor silicon complex monolayers. Accordingly, in the example of Table VIbelow, the oxidant of the fourth phase 223 differs from the oxidant ofthe third phase 219, at least for those cycles in which themetal/silicon source of the third phase 219 differs from themetal/silicon source of the first phase 207.

[0070] For a roughly one-to-one ratio of the different metals ormetal:silicon in the resultant dielectric, the cycle 215 is repeated, asshown. In the example of Table VI below, for example, repeated cycleswith metal, oxygen, silicon and oxygen phases, in sequence, produces ametal silicate layer. Alternatively, the illustrated cycle 215 for aternary dielectric can be conducted after a string of binary cycles 115(FIG. 4A), depending upon the desired ratio of the different metals inthe resultant ternary dielectric. Conversely, a binary cycle 115 (FIG.4A) can be conducted after a string of ternary cycles 215. Softwarecontrolling the gas flow valves can be programmed, for example, toconduct a one ternary cycle 215 after every three binary cycles 115(FIG. 4A). Such a process would produce roughly a 3:1 ratio of a firstmetal to a second metal (or silicon) in the dielectric layer. Theskilled artisan will appreciate, in view of the disclosure herein, thatthe actual ratio would depend both upon the frequency with which thesecond metal is substituted in the process and upon the relativephysical size of the chemisorbed molecules.

[0071] Though both the binary and ternary processes are illustrated inFIGS. 4A and 4B with an initial metal/silicon phase and a subsequentoxygen phase in the examples below, it will be understood that thecycles can begin with an oxygen phase, depending upon the lower surfacesand phase chemistries.

[0072] Methods of Forming Metal Oxide Dielectrics

[0073]FIG. 5 and Tables I to V below illustrate exemplary processes forforming metal oxide dielectrics over the HSG silicon of the bottomelectrode. Table I exemplifies forming an oxide of a non-transitionmetal (e.g., aluminum); Tables II and III exemplify forming an oxide ofa Group V transition metal (e.g., vanadium, niobium, tantalum); andTables IV and V exemplify forming an oxide of Group IV transition metals(e.g., titanium, zirconium, hafnium). For simplicity, like referencenumerals are employed to refer to the phases and steps of the metaloxide examples (FIG. 5) that correspond to the general description ofFIG. 4A.

[0074] With reference now to FIG. 5, a gas flow sequence is representedin accordance with a particular embodiment. In the illustrated example,a high k dielectric, and more particularly a high k metal oxide, isformed by supplying the workpiece with a metal source gas alternatelywith an oxygen source gas. The first or metal phase 107 of each cyclechemisorbs a layer of metal-containing material, desirably in theabsence of the oxygen source gas. The second or oxygen phase 111 of eachcycle reacts or adsorbs an oxygen-containing material on the depositedmetal-containing layer, desirably in the absence of the metal sourcegas. It will be understood that, in other arrangements, the order of thephases can be reversed, and that the reactant removal or purge steps canbe considered part of the preceding or subsequent reactant pulse.

[0075] Surfaces upon which the dielectric material is to be formed areinitially terminated to provide a surface that is reactive with themetal source gas. In the preferred embodiments, the exposed surfacesupon which deposition is desired include HSG silicon with OH terminatingtails (see FIG. 7) and silicon nitride (see FIG. 8).

[0076] Most preferably, the metal phase 107 is self-limiting, such thatno more than about one atomic monolayer is deposited during the firstphase. Desirably, a volatile metal source gas is provided in a pulse104. Exemplary metal source gases include: trimethyl aluminum (TMA or(CH₃)₃Al); aluminum chloride (AlCl₃); aluminum betadiketonates (e.g.,Al(acac)₃); tantalum ethoxide (Ta(OCH₂CH₃)₅); tantalum pentachloride(TaCl₅); pentakis(dimethylamino) tantalum (Ta[N(CH₃)]₅); zirconiumtetrachloride (ZrCl₄); zirconium butoxide (ZrOCH₂CH₂CH₃)₄); titaniumtetrachloride (TiCl₄); titanium isopropoxide (Ti[OCH(CH₃)₃]₄);tetrakis(dimethylamino) titanium (Ti[N(CH₃)₂]₄); tetrakis(dimethylamino) titanium (Ti[N(CH₅)₂]₄ tungsten hexafluoride (WF₆);3-aminopropyltriethoxysilane (NH₂CH₂CH₂CH₂—Si(O—CH₂CH₃)₃ or AMTES);3-aminopropyltrimethoxsilane (NH₂CH₂CH₂CH₂—Si(O—CH₃)₃ or AMTMS);dichlorosilane (DCS); trichlorosilane (TCS); vanadium trichloride(VCl₃); vanadium acetylacetonate (V(acac)₃); niobium pentachloride(NbCl₅); niobium ethoxide (Nb(OCH₂CH₃)₅); hafnium tetrachloride (HfCl₄),etc.

[0077] After a sufficient time for the metal source gas to saturatesurfaces of the bottom electrode, shutting off the flow of the metalsource gas ends the metal pulse 104. Preferably, carrier gas continuesto flow in a purge step 106 until the metal source gas is purged fromthe chamber.

[0078] During the pulse 104, the metal source gas reacts with exposedsurfaces of the workpiece to deposit or chemisorb a “monolayer” of metalcomplex. While theoretically the reactants will chemisorb at eachavailable site on the exposed layer of the workpiece, physical size ofthe adsorbed complex (particularly with large terminating ligands) willgenerally limit coverage with each cycle to a fraction of a monolayer.In the example of Table I, the ALD process grows metal oxide layers atroughly 1 Å/cycle, such that a full monolayer effectively forms frommaterial deposited approximately every 3 cycles for Al₂O₃, which has abulk lattice parameter of about 3 Å. Each cycle is represented by a pairof metal source gas and oxygen source gas pulses. “Monolayer,” as usedherein, therefore represents a fraction of a monolayer duringdeposition, referring primarily to the self-limiting effect of the pulse104.

[0079] In particular, the metal-containing species provided to theworkpiece is self-terminating such that the adsorbed complex surfacewill not further react with the metal source gas. In the examples setforth below, TMA (Table I) leaves a monolayer of methyl-terminatedaluminum. Tantalum ethoxide (Table II) leaves a monolayer of ethoxidetantalum. Similarly, other volatile metal halides will leavehalide-terminated surfaces, and metallorganic precursors will leavesurface terminated with organic ligands. Such surfaces do not furtherreact with the metal source or other constituents of the reactant flowduring the metal source gas pulse 104. Because excess exposure to thereactants does not result in excess deposition, the chemistry during themetal phase 107 of the process is said to be saturative orself-limiting. Despite longer exposure to a greater concentration ofreactants, deposition on upper surfaces of HSG silicon grains does notexceed deposition in neck regions between grains.

[0080] In a second phase 111 of the cycle 115, a pulse 108 of an oxygensource gas is then provided to the workpiece. In the illustratedexamples, the oxygen source gas comprises water vapor (H₂O) or ozone.Other suitable oxidants include: hydrogen peroxide (H₂O₂); methanol(CH₃OH); ethanol (CH₃CH₂OH), nitrous oxide (N₂O, NO₂); O radicals; etc.Radicals can be provided by remote plasma sources connected to thereaction chamber, and an ozone generator can similarly provide ozone(O3). Preferably, the second phase 111 is maintained for sufficient timeto fully expose the monolayer of metal complex left by the first phase107 to the oxygen source gas. After a sufficient time for the oxygensource gas to saturate the metal-containing monolayer over the HSGsilicon layer, shutting off the flow of the oxygen source gas ends theoxygen pulse 108. Preferably, carrier gas continues to flow in a purgestep 110 until the oxygen source gas is purged from the chamber.

[0081] During the oxygen pulse 108, the oxygen source gas reacts with orchemisorbs upon the self-terminated metal complex monolayer left by thefirst phase 107. In the illustrated embodiments, this chemisorptioncomprises a saturative ligand-exchange reaction, replacing the organicligand or halide termination of the metal-containing monolayer withoxygen or an oxygen complex. Metal oxide is thereby formed, preferablyin a single monolayer. Desirably, the process leaves a stoichiometricmetal oxide, with hydroxyl and oxygen bridge termination. As discussedwith respect to the metal phase 107, the monolayer need not occupy allavailable sites, due the physical size of the adsorbed complex. However,the second phase 111 also has a self-limiting effect.

[0082] In particular, the oxygen source gas reacts with the ligand ofthe metal complex chemisorbed onto the workpiece surface during theprevious pulse of metal source gas. The reaction is also surfacelimiting or terminating, since the oxidant during the pulse 108 will notreact with the hydroxyl and oxygen bridge termination of the metal oxidemonolayer. Moreover, temperature and pressure conditions are arranged toavoid diffusion of the oxidant through the metal monolayer to underlyingmaterials. Despite longer exposure to a greater concentration ofreactants in this saturative, self-limiting reaction phase 111, thethickness of the metal oxide formed on upper surfaces of the HSG silicongrains does not exceed the thickness of the metal oxide formed in theneck regions between grains.

[0083] The metal phase 107 (including metal source pulse 104 and purge106) and oxygen phase 108 (including oxygen source pulse 108 and purge110) together define a cycle 115 that is repeated in an ALD process.After the initial cycle 115, a second cycle 115 a is conducted, whereina metal source gas pulse 104 a is again supplied. The metal source gaschemisorbs a metal complex on the surface of the metal oxide formed inthe previous cycle 115. The metal-containing species readily react withthe exposed surface, depositing another monolayer or fraction of amonolayer of metal complex and again leaving a self-terminated surfacethat does not further react with the metal source gas. Metal source gasflow 104 a is stopped and purged 106 a from the chamber, and a secondphase 11 a of the second cycle 115 a provides oxygen source gas tooxidize the second metal monolayer.

[0084] The cycle 115 a is repeated at least about 10 times, and morepreferably at least about 20 times, until a sufficiently thick metaloxide is formed to avoid leakage during memory cell operation.Advantageously, layers having a uniform thickness between about 10 Å and200 Å, and more preferably between about 25 Å and 100 Å, can be formedwith near perfect step coverage by the methods of the preferredembodiments.

[0085] The tables below provide exemplary process recipes for formingmetal oxide and ternary dielectric layers suitable for capacitordielectric applications in DRAM memory cells for ultra large scaleintegrated processing. The dielectrics are particularly suited todeposition over HSG silicon. Each of the process recipes represents onecycle in a single-wafer process module. In particular, the illustratedparameters were developed for use in the single-wafer ALD modulecommercially available under the trade name Pulsar 2000™, availablecommercially from ASM Microchemistry Ltd. of Finland.

[0086] Note that the parameters in the tables below are exemplary only.Each process phase is desirably arranged to saturate the bottomelectrode surfaces. Purge steps are arranged to remove reactants betweenreactive phases from the reaction chamber. The illustrative ALDprocesses achieve better than about 95% thickness uniformity, and morepreferably greater than about 98% thickness uniformity over HSG grainswith average gain sizes of about 400 Å. Thickness uniformity, as usedherein, is defined as the percentage of a thickness minimum as apercentage of the thickness maximum. In view of the disclosure herein,the skilled artisan can readily modify, substitute or otherwise alterdeposition conditions for different reaction chambers and for differentselected conditions to achieve saturated, self-terminating phases atacceptable deposition rates.

[0087] Advantageously, the ALD processes described herein are relativelyinsensitive to pressure and reactant concentration, as long as thereactant supply is sufficient to saturate the textured surfaces.Furthermore, the processes can operate at low temperatures. Workpiecetemperature is preferably maintained throughout the process betweenabout 150° C. and 350° C. to achieve relatively fast deposition rateswhile conserving thermal budgets. More preferably, the temperature ismaintained between about 220° C. and 300° C., depending upon thereactants. Pressure in the chamber can range from the milliTorr range tosuper-atmospheric, but is preferably maintained between about 1 Torr and500 Torr, more preferably between about 1 Torr and 10 Torr. TABLE IAl₂O₃ Carrier Reactant Flow Flow Temperature Pressure Time Phase (sccm)Reactant (sccm) (° C.) (Torr) (sec) metal 400 TMA 20 300 5 0.1 purge 400— — 300 5 0.2 oxidant 400 H₂O 40 300 5 0.1 purge 400 — — 300 5 0.6

[0088] Table I above presents parameters for ALD of an aluminum oxide(Al₂O₃) dielectric over HSG silicon. The exemplary metal source gascomprises trimethyl aluminum (TMA), the carrier gas comprises nitrogen(N₂) and the oxygen source gas preferably comprises water vapor (H₂O).The temperature during the process is preferably kept between about 150°C. and 350° C., and more preferably at about 300° C.

[0089] In the first phase of the first cycle, TMA chemisorbs upon theHSG silicon surfaces of the bottom electrode. The metal source gaspreferably comprises a sufficient percentage of the carrier flow, giventhe other process parameters, to saturate the bottom electrode surfaces.A monolayer of aluminum complex is left upon the HSG silicon surfaces,and this monolayer is self-terminated with methyl tails.

[0090] After the TMA flow is stopped and purged by continued flow ofcarrier gas, a pulse of H₂O is supplied to the workpiece. The waterreadily reacts with the methyl-terminated surface of the metal monolayerin a ligand-exchange reaction, forming a monolayer of aluminum oxide(Al₂O₃). The reaction is limited by the number of available metalcomplexes previously chemisorbed. The reaction is furthermoreself-limiting in that neither water nor the carrier gas further reactswith the hydroxyl and oxygen bridge termination of the resultingaluminum oxide monolayer. The preferred temperature and pressureparameters, moreover, inhibit diffusion of water or reaction by-productsthrough the metal monolayer.

[0091] In the next cycle, the first phase introduces TMA, which readilyreacts with the surface of the aluminum oxide monolayer, again leaving amethyl-terminated aluminum layer above the first metal oxide layer. Thesecond phase of the second cycle is then as described with respect tothe first cycle. These cycles are repeated until the desired thicknessof aluminum oxide is formed.

[0092] In the illustrated embodiment, carrier gas continues to flow at aconstant rate during both phases of each cycle. It will be understood,however, that reactants can be removed by evacuation of the chamberbetween alternating gas pulses. In one arrangement, the preferredreactor incorporates hardware and software to maintain a constantpressure during the pulsed deposition. The disclosures of U.S. Pat. No.4,747,367, issued May 31, 1988 to Posa and U.S. Pat. No. 4,761,269,issued Aug. 2, 1988 to Conger et al., are incorporated herein byreference.

[0093] Radicals provided by plasma generators can facilitate depositionof metal-containing layers at the low temperatures of ALD processing.Structures and methods of depositing layers with radical enhancement areprovided in patent application having Ser. No. 09/392,371, filed Sep. 8,1999 and entitled IMPROVED APPARATUS AND METHOD FOR GROWTH OF A THINFILM, the disclosure of which is incorporated by reference hereinabove.Another exemplary ALD process flow is provided in U.S. Pat. No.5,916,365 to Sherman, issued Jun. 29, 1999, the disclosure of which isincorporated herein by reference. TABLE II Ta₂O₅ Carrier ReactantTemper- Flow Flow ature Pressure Time Phase (sccm) Reactant (sccm) (°C.) (Torr) (sec) metal 400 Ta 40 220 5 1 (OCH₂CH₃)₅ purge 400 — — 220 51 oxidant 400 O₃ 100 220 5 1 purge 400 — — 220 5 2

[0094] Table II above presents parameters for ALD of a tantalum oxide(Ta₂O₅) over HSG silicon of a capacitor bottom electrode. Preferably,the illustrated dielectric deposition is preceded by formation of abarrier layer to protect the HSG silicon from oxidation. In theillustrated embodiment, a dielectric barrier is formed, specificallycomprising silicon nitride (Si₃N₄). Advantageously, silicon nitride canbe formed over HSG silicon with near perfect conformality by thermallynitriding the silicon surfaces. In other arrangements, a thin oxidelayer can be first grown (e.g., by thermal oxidation) over the HSGsilicon, followed by thermal nitridation of the oxide surface, as isknown in the art.

[0095] Following formation of the barrier layer, Ta₂O₅ is formed in anALD process. As indicated in Table II, the illustrated metal source gascomprises tantalum ethoxide (Ta(OCH₂CH₃)₅); the carrier gas comprisesnitrogen (N₂); and the oxygen source gas preferably comprises ozone(O₃). The temperature during the process is preferably kept betweenabout 150° C. and 300° C., and more preferably at about 220° C.

[0096] In the first phase of the first cycle, tantalum ethoxidechemisorbs upon the nitridized surfaces of the HSG silicon. The metalsource gas preferably comprises a sufficient percentage of the carrierflow, given the other process parameters, to saturate the nitride-coatedHSG silicon surfaces. A monolayer of tantalum complex is left upon thetextured surfaces, and this monolayer is self-terminated with ethoxidetails.

[0097] After the metal source gas flow is stopped and purged bycontinued flow of carrier gas, a pulse of ozone is supplied to theworkpiece. Ozone preferably comprises a sufficient percentage of thecarrier flow, given the other process parameters, to saturate thesurface of the metal-containing monolayer. The ozone readily reacts withthe ethoxide-terminated surface of the metal-containing monolayer in aligand-exchange reaction, forming a monolayer of tantalum oxide (Ta₂O₅).The reaction is limited by the number of available metal complexespreviously chemisorbed. Neither ozone nor the carrier gas further reactswith the resulting tantalum oxide monolayer. Ozone causes the organicligand to burn, liberating CO₂ and H₂O, and the monolayer is left withhydroxyl and oxygen bridge termination. The preferred temperature andpressure parameters, moreover, inhibit diffusion of ozone and reactionby-products through the metal monolayer.

[0098] In the next cycle, the first phase introduces tantalum ethoxide,which readily reacts with the surface of the tantalum oxide monolayer,again leaving an ethoxide-terminated tantalum layer. The second phase ofthe second cycle is then as described with respect to the first cycle.These cycles are repeated until the desired thickness of tantalum oxideis formed. Preferably, between about 80 and 200 cycles are conducted togrow between about 40 Å and 100 Å of Ta₂O₅. More preferably, betweenabout 80 and 100 cycles are conducted to grow between about 40 Å and 50Å

[0099] In the illustrated embodiment, carrier gas continues to flow at aconstant rate during both phases of each cycle. It will be understood,however, that reactants can be removed by evacuation of the chamberbetween alternating gas pulses. In one arrangement, the preferredreactor incorporates hardware and software to maintain a constantpressure during the pulsed deposition. The disclosures of U.S. Pat. No.4,747,367, issued May 31, 1988 to Posa and U.S. Pat. No. 4,761,269,issued Aug. 2, 1988 to Conger et al., are incorporated herein byreference.

[0100] An amorphous Ta₂O₅ dielectric layer is left with only traceamounts of carbon. This layer can be annealed for a crystallizeddielectric, if desired. The dielectric constant of the layer is betweenabout 20 and 25. TABLE III Ta₂O₅ Carrier Reactant Flow Flow TemperaturePressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400TaCl₅ 40 300 5 0.5 purge 400 — — 300 5 0.5 oxidant 400 H₂O 40 300 5 0.5purge 400 — — 300 5 0.5

[0101] Table III above presents parameters for another ALD process fordepositing tantalum oxide (Ta₂O₅) over HSG silicon of a capacitor bottomelectrode. Following formation of the silicon nitride barrier layer, asdescribed above, Ta₂O₅ is formed in an ALD process. As indicated inTable III, the preferred metal source gas comprises tantalum chloride(TaCl₅); the carrier gas again comprises nitrogen (N₂); and the oxygensource gas preferably comprises water vapor (H₂O). Temperatures duringthe process are preferably between about 150° C. and 300° C., and morepreferably about 300° C.

[0102] In the first phase of the first cycle, tantalum chloridechemisorbs upon the silicon nitridized surfaces of the HSG. The metalsource gas preferably comprises a sufficient percentage of the carrierflow, given the other process parameters, to saturate the nitride-coatedHSG silicon surfaces. A monolayer of tantalum complex is left upon thetextured surfaces, and this monolayer is self-terminated with chloridetails.

[0103] After the TaCl₅ flow is stopped and purged by continued flow ofcarrier gas, a pulse of water vapor is supplied to the workpiece. Watervapor preferably comprises a sufficient percentage of the carrier flow,given the other process parameters, to saturate the surface of themetal-containing monolayer. The water readily reacts with thechloride-terminated surface of the metal-containing monolayer in aligand-exchange reaction, forming a monolayer of tantalum oxide (Ta₂O₅).The reaction is limited by the number of available metal chloridecomplexes previously chemisorbed. Neither water nor the carrier gasfurther reacts with the hydroxyl and oxygen bridge termination of theresulting tantalum oxide monolayer. The preferred temperature andpressure parameters, moreover, inhibit diffusion of water and reactionby-products through the metal monolayer.

[0104] In the next cycle, the first phase introduces TaCl₅, whichreadily reacts with the surface of the tantalum oxide monolayer, againleaving a chloride-terminated tantalum layer. The second phase of thesecond cycle is then as described with respect to the first cycle. Thesecycles are repeated until the desired thickness of tantalum oxide isformed, as described with respect to the preceding example.

[0105] As mentioned above, the chamber can be evacuated to removereactants between pulses, rather than purged by a steady carrier gasflow as shown, though inter-pulse purging is preferred.

[0106] An amorphous Ta₂O₅ dielectric layer is left with only traceamounts of chlorine. This layer can be annealed for a crystallizeddielectric, if desired. The dielectric constant of the layer is betweenabout 20 and 25. TABLE IV ZrO₂ Carrier Reactant Flow Flow TemperaturePressure Time Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 400ZrCl₄ 5 300 5 0.5 purge 400 — — 300 5 3 oxidant 400 H₂O 40 300 5 2 purge400 — — 300 5 6

[0107] Table IV above presents parameters for ALD of zirconium oxide(ZrO₂). As noted, the metal source comprises zirconium chloride (ZrCl₄);the carrier gas comprises nitrogen (N₂); and the oxygen source gaspreferably comprises water vapor (H₂O). During each of the reactionphases, the reactants are supplied in sufficient quantity for the givenother parameters to saturate the surface.

[0108] Temperatures during the process preferably fall between about200° C. and 500° C. For an amorphous ZrO₂ layer, the temperature is morepreferably at the low end of this range, between about 200° C. and 250°C., and most preferably at about 225° C. For a crystalline film, thetemperature is more preferably at the high end of this range, betweenabout 250° C. and 500° C., and most preferably about 300° C. As will beappreciated by the skilled artisan, however, mixtures of amorphous andcrystalline composition result at the boundary of these two regimes. Theillustrated process produces a largely crystalline ZrO₂ film.

[0109] In this case, the metal monolayer formed in the metal phase isself-terminated with chloride, which does not readily react with excessZrCl₄ under the preferred conditions. The preferred oxygen source gas,however, reacts with or adsorbs upon the chloride-terminated surfaceduring the oxygen phase in a ligand-exchange reaction limited by thesupply of zirconium chloride complexes previously adsorbed. Moreover,oxidation leaves a hydroxyl and oxygen bridge termination that does notfurther react with excess oxidant in the saturative phase.

[0110] Preferably, between about 30 and 80 cycles are conducted to growbetween about 20 Å and 60 Å of ZrO₂. More preferably, between about 30and 50 cycles are conducted to grow between about 20 Å and 40 Å. Thedielectric constant of the layer is between about 18 and 24. TABLE VTiO₂ Carrier Reactant Flow Flow Temperature Pressure Time. Phase (sccm)Reactant (sccm) (° C.) (Torr) (sec) metal 400 TiCl₄ 20 300 5 0.5 purge400 — — 300 5 3 oxidant 400 H₂O 40 300 5 2 purge 400 — — 300 5 6

[0111] Table V above presents parameters for ALD of titanium oxide(TiO₂). As noted, the metal source comprises titanium tetrachloride(TiCl₄); the carrier gas comprises nitrogen (N₂); and the oxygen sourcegas preferably comprises water vapor (H₂O). During each of the reactionphases, the reactants are supplied in sufficient quantity for the givenother parameters to saturate the surface.

[0112] As described with respect to ZrO₂ in the preceding example,temperatures is preferably kept at a level between about 200° C. and500° C. In the illustrated embodiment, however, the illustratedembodiment employs a temperature between about 250° C. and 500° C., andmost preferably about 300° C.

[0113] In this case, the metal monolayer formed in the metal phase isself-terminated with chloride, which does not readily react with TiCl₄under the preferred conditions. The preferred oxygen source gas,however, reacts with or adsorbs upon the chloride-terminated surfaceduring the oxygen phase in a reaction limited by the supply of titaniumchloride complexes previously adsorbed. Moreover, oxidation leaves ahydroxyl and oxygen bridge and termination that does not further reactwith excess oxidant in the saturative phase.

[0114] Preferably, between about 30 and 80 cycles are conducted to growbetween about 20 Å and 60 Å of TiO₂. More preferably, between about 30and 50 cycles are conducted to grow between about 20 Å and 40 Å. Thedielectric constant of the layer is between about 15 and 25.

[0115] Method of Forming Ternary Dielectric Layers

[0116] As discussed with respect to FIG. 4B, the principles of ALDdescribed above with respect to metal oxide capacitor dielectrics, canalso be extended to depositing ternary materials and more complexmaterials.

[0117] With reference to FIG. 6, a gas flow schematic is shown for ageneral process of forming ternary structures, specifically for formingmixed or compound metal oxides or metal silicates. Though the example ofTable VI below relates to a metal silicate layer, formed bymetal/oxygen1/silicon/oxygen2 phases, in that order, the skilled artisanwill readily appreciate that the disclosed sequence can be altered forsilicate materials (e.g., silicon/oxygen/metal/oxygen) or adapted forcomplex metal oxides (e.g., first metal/oxygen/second metal/oxygen).Furthermore, the illustrated sequence can be extended to encompass morecomplex materials incorporating multiple elements. For convenience, thereference numerals of FIG. 4B are utilized to refer to like processsteps, phases and sequences.

[0118] As illustrated, the process comprises four phases to each cycle,wherein each phase comprises a reactant phase and a purge phase. A firstmetal or silicon phase 207 is followed by a first oxygen phase 211, asecond metal or silicon phase 219, and a second oxygen phase 223, insequence. The cycle is then repeated. As previously noted, in otherarrangements, the first or fourth phase can be omitted every cycle orevery few cycles, if a low oxygen content is desired. In such a case,chemistries should be selected to permit reaction between depositedmonolayers and subsequent chemistries. As will be better understood fromthe discussion of Table VI below, the first oxygen source (in the secondphase 211) can be, but is not necessarily, the same as the second oxygensource (in the fourth phase 223). After four phases 207, 211, 219, 223complete the first cycle 215, a second, similar cycle 215 a can beconducted to continue ternary growth. These cycles 215, 215 a continuesuntil the ternary material of interest is thick enough to avoid currentleakage but thin enough to exhibit high capacitance.

[0119] In general, the process enables dielectric layers having mixedmetal oxides, ternary metal oxide compounds, metal silicates, or morecomplex dielectric materials. For example, TiO₂ can be mixed with Ta₂O₅by alternating cycles. A largely binary cycle can be repeated severaltimes between ternary cycles, if only a slight doping effect is desired.The example of Table VI below, however, a zirconium silicon oxide or“zirconium silicate” layer is illustrated. TABLE VI Zirconium siliconoxide Carrier Reactant Flow Flow Temperature Pressure Time Phase (sccm)Reactant (sccm) (° C.) (Torr) (sec) metal 400 ZrCl₄ 40 300 5 0.5 purge400 — — 300 5 3 oxygen 400 H₂O 40 300 5 2 purge 400 — — 300 5 6 silicon400 AMTMS 40 300 5 1 purge 400 — — 300 5 2 oxygen 400 O₃ 40 300 5 3.5purge 400 — — 300 5 1

[0120] Table VI above presents parameters for ALD of zirconium siliconoxide or zirconium silicate (ZrSi_(x)O_(y)). As noted in Table VI, thefirst reactant source comprises a source of metal for the compound to beformed. In particular, zirconium chloride (ZrCl₄) supplies the metal.Other process gases include the carrier gas, comprising nitrogen (N₂) inthe illustrated embodiment, and a silicon source gas, preferablycomprising 3-aminopropyltrimethoxsilane (NH₂CH₂CH₂CH₂—Si(O—CH₃)₃ orAMTMS). Other suitable silicon gas sources include various organosilaneand halosilane gases. During each of the reaction phases, the reactantsare supplied in sufficient quantity for the given other parameters tosaturate the surface.

[0121] sublayers. An exemplary stack includes between about 5 and 40 andmore preferably about 10 alternating layers of Ta₂O₅ and TiO₂.

[0122] Preferably at least one of the sublayers, and more preferably allof the sublayers, is formed by ALD in accordance with the methodsdisclosed above. FIG. 9 illustrates an exemplary capacitor formed bythis process, discussed in more detail below.

[0123] In the illustrated embodiments, a process as described abovepreferably conducted for between about 10 and 100 cycles, producing ahigh k dielectric layer having a thickness of between about 5 Å and 50 Å(assuming about 0.5 Å/cycle). Another dielectric material is preferablyalso deposited, and also formed to thickness of between about 5 Å and 50Å. In an exemplary process flow, the process of Table II above isalternated, after forming about 5 Å of Ta₂O₅, with the process of TableV, whereby about 5 Å of TiO₂ is formed, and so on until a suitablethickness is reached for memory cell capacitor applications.

[0124] As with the mixed or compound layers described with respect toTable VI, dielectric stacks or “nanolaminates” so formed tend to exhibitenhanced dielectric properties and more stable structures in contactwith silicon.

[0125] Methods of Forming Top Electrode Materials

[0126] After formation of the dielectric layer, a top electrode isformed over the capacitor dielectric. If the top electrode does notperfectly conform to the dielectric, the full benefit of the texturedbottom electrode and conformal dielectric is not realized. Accordingly,the top electrode formed over the capacitor dielectric preferablyincludes at least one conductive thin film that is also deposited withnear perfect conformality by an ALD process.

[0127] The top electrode is desirably relatively thick for high lateralconductivity across a memory array and/or to land contacts thereuponwithout risking spikes through the capacitor dielectric. However, thepreferred alternating deposition process need not form the fullthickness of the top electrode. Rather, one or more initial thinconductive layers can be conformally formed by the preferred alternatingprocess, followed by convention deposition for the bulk of the topelectrode thickness. The alternating process provides a conductivecoating in continuous direct contact with the capacitor dielectric, thusconforming to the

[0128] In the illustrated sequence, a metal phase is followed by anoxygen phase, which is in turn followed by a silicon phase and a secondoxygen phase. The cycle then repeats. While the illustrated exampleemploys two different oxygen source gases for the first and secondoxygen phases (second and fourth phases) of each cycle, the same oxygensource could alternatively be employed for both phases.

[0129] During the metal phase, a zirconium-containing monolayer isself-terminated with chloride tails. The termination of this monolayerdoes not readily react with ZrCl₄ under the preferred conditions. In thenext phase, water vapor oxidizes the metal containing monolayer,replacing chloride termination with hydroxyl and oxygen bridgetermination. Then the preferred silicon source gas reacts with oradsorbs upon the hydroxyl and oxygen bridge termination during thesilicon phase in a ligand-exchange reaction limited by the supply ofmetal oxide complexes previously adsorbed. Moreover, the preferredsilicon source gas leaves an organic (ethoxide) or halide (chloride)termination that does not further react with excess silicon ethoxide inthe saturative phase. Finally, ozone oxidizes the previously adsorbedsilicon-containing monolayer to leave a ternary oxide.

[0130] As will be appreciated by the skilled artisan, ternary structuressuch as the illustrated zirconium silicate (ZrSi_(x)O_(y)) layeradvantageously exhibit higher dielectric constants, less operationalleakage, and more stable structures interfacing with silicon. The ratioof Zr:Si can be controlled for optimal properties, depending upon therelative number of four-phase cycles conducted as compared to two-phase(simple metal) in the same process. Accordingly, the zirconium silicateis not necessarily stoichiometric.

[0131] Preferably, between about 20 and 100 cycles are conducted to growbetween about 20 Å and 100 Å of ZrSi_(x)O_(y). More preferably, betweenabout 20 and 40 cycles are conducted to grow between about 20 Å and 40Å. The dielectric constant of the layer is between about 10 and 15.

[0132] Method of Forming Dielectric Stacks

[0133] In contrast to the mixed or compound structures produced by theprocess of FIGS. 4B and 6, the capacitor dielectric can also comprise astack of distinct dielectric undulations of the underlying texturedbottom electrode. The remainder of the top electrode, deposited byconventional means, need not be conformal. Furthermore, voids can betolerated between the initial, conformal thin film(s) and the remainderof the top electrode thickness, as long as the intitial thin film isadequately connected into the circuitry of the integrated circuit.

[0134] The initial conductive thin film(s) can comprise any suitableconductive material, including silicon, metal nitrides and elementalmetals, composites thereof and nanolaminates thereof. Depending upon thematerial of the dielectric capacitor, a barrier layer may be desiredover the dielectric. Particularly when employing Ta₂O₅, a barrierthereover prevents oxidation of the remainder of the top electrode. Theremainder of the top electrode can then be completed by conventionaldeposition of a conductive film, such as silicon or metal.

[0135] In the example of Table VII below, the top electrode comprises aconductive metal nitride, which can serve as a barrier layer over Ta₂O₅,deposited by an ALD process to conformally and continuously coat thecapacitor dielectric. The example of Table VIII below the top electrodecomprises an elemental metal layer, which can overlie or replace thebarrier of Table VII, also formed by an ALD process. TABLE VII TiNCarrier Reactant Flow Flow Temperature Pressure Time Phase (sccm)Reactant (sccm) (° C.) (Torr) (sec) metal 400 TiCL₄ 20 400 10 1 purge400 — — 400 10 1 nitrogen 400 NH₃ 100 400 10 2 purge 400 — — 400 10 4

[0136] Table VII above presents parameters for ALD of a conformal metalnitride barrier over a capacitor dielectric. The process is similar tothat of FIGS. 4A and 5, except that the oxygen source gas is substitutedwith a nitrogen source gas. Accordingly, one of the reactant speciespreferably includes a metal-containing species with an organic or halideligand, while a second reactant species includes a nitrogen-containingspecies. In the illustrated embodiment, the metal film comprises atitanium nitride (TiN) film formed by ALD in alternating, self-limitingmetal and nitrogen phases separated by purge steps. In the example ofTable VII, the exemplary metal source gas comprises titaniumtetrachloride (TiCl₄), the carrier gas comprises nitrogen (N₂) and thenitrogen source gas preferably comprises ammonia (NH₃).

[0137] In the first phase of the first cycle, TiCl₄ chemisorbs upon thehydroxyl and oxygen bridge termination of the deposited high kdielectric. The metal source gas preferably comprises a sufficientpercentage of the carrier flow, given the other process parameters, tosaturate the dielectric surfaces. A monolayer of titanium complex isleft upon the dielectric, and this monolayer is self-terminated withhalide tails.

[0138] Desirably, the reactor includes a catalyst to convert the metalsource gas to a smaller and/or more reactive species. In the illustratedembodiment, the preferred reaction chamber comprises titanium walls,which advantageously convert TiCl₄ to TiCl₃ ⁺. The smaller speciesreadily diffuse into confined spaces, occupy more reactive sites percycle and more readily chemisorb onto the active sites. Accordingly, thecatalyst enables faster deposition rates. The skilled artisan willreadily appreciate that other catalysts can be employed for otherchemistries.

[0139] After the TiCl₄ flow is stopped and purged by continued flow ofcarrier gas, a pulse of NH₃ is supplied to the workpiece. Ammoniapreferably comprises a sufficient percentage of the carrier flow, giventhe other process parameters, to saturate the surface of themetal-containing monolayer. The NH₃ readily reacts with thechloride-terminated surface of the metal monolayer in a ligand-exchangereaction, forming a monolayer of titanium nitride (TiN). The reaction islimited by the number of available metal chloride complexes previouslychemisorbed. Neither ammonia nor the carrier gas further reacts with theresulting titanium nitride monolayer. The (preferred temperature andpressure parameters, moreover, inhibit diffusion of ammonia through themetal monolayer.

[0140] In the next cycle, the first phase introduces TiCl₄, whichreadily reacts with the surface of the titanium nitride monolayer, againleaving a chloride-terminated titanium layer. The second phase of thesecond cycle is then as described with respect to the first cycle. Thesecycles are repeated until a thickness of titanium nitride sufficient toperform a barrier function is formed. Preferably between about 5 nm and50 nm, more preferably between about 10 nm and 30 nm of metal nitride isformed in this manner.

[0141] In the illustrated embodiment, carrier gas continues to flow at aconstant rate during both phases of each cycle. It will be understood,however, that reactants can be removed by evacuation of the chamberbetween alternating gas pulses. In one arrangement, the preferredreactor incorporates hardware and software to maintain a constantpressure during the pulsed deposition. The disclosures of U.S. Pat. No.4,747,367, issued May 31, 1988 to Posa and U.S. Pat. No. 4,761,269,issued Aug. 2, 1988 to Conger et al., are incorporated herein byreference. TABLE VIII Carrier Reactant Flow Flow Temperature PressureTime Phase (sccm) Reactant (sccm) (° C.) (Torr) (sec) metal 600 WF₆ 50400 10 0.25 purge 600 — — 400 10 0.5 reduce 600 TEB 40 400 10 0.1 purge600 — — 400 10 0.8

[0142] Table VIII above presents parameters for ALD of a conformalelemental metal layer over a capacitor dielectric. The process can beconducted immediately following formation of a barrier layer (see TableVII) or directly over the capacitor dielectric. The process is alsosimilar to that of FIGS. 4A and 5, except that the oxygen source gas issubstituted with a reducing agent. Accordingly, one of the reactantspecies preferably includes a metal-containing species with an organicor halide ligand, while a second reactant species includes a strongreducing agent. In the illustrated embodiment, the metal film comprisesa tungsten (W) layer formed by ALD, in alternating metal and reducingphases separated by purge steps. In the example of Table VIII, the metalsource gas comprises tungsten hexafluoride (WF₆), the carrier gascomprises nitrogen gas (N₂) and the reducing agent comprises triethylboron ((CH₃CH₂)₃B) or TEB.

[0143] In the first phase of the first cycle, WF₆ chemisorbs upon thehydroxyl and oxygen bridge termination of the deposited high kdielectric, or upon the termination of a previously formed barrierlayer. The metal source gas preferably comprises a sufficient percentageof the carrier flow, given the other process parameters, to saturate thedielectric surfaces. A monolayer of tungsten complex is left upon thedielectric, and this monolayer is self-terminated with halide tails.

[0144] After the WF₆ flow is stopped and purged by continued flow ofcarrier gas, a pulse of TEB is supplied to the workpiece. TEB preferablycomprises a sufficient percentage of the carrier flow, given the otherprocess parameters, to saturate the surface of the metal-containingmonolayer. The TEB readily reduces the halide-terminated surface of themetal-containing monolayer, leaving a monolayer of tungsten. The numberof available metal halide complexes previously chemisorbed limits thereaction. Neither TEB nor the carrier gas further reacts with theresulting tungsten monolayer. The preferred temperature and pressureparameters, moreover, inhibit diffusion of TEB through the metalmonolayer.

[0145] In the next cycle, the first phase introduces WF₆, which readilyreacts with the surface of the tungsten monolayer, again leaving ahalide-terminated tungsten layer. The second phase of the second cycleis then as described with respect to the first cycle. These cycles arerepeated until the desired thickness of tungsten is formed. Preferablybetween about 5 nm and 50 nm, more preferably between about 10 nm and 30nm of tungsten ensures continuous and conformal coverage to take fulladvantage of the high surface area of the underlying bottom electrodeand capacitor dielectric.

[0146] In the illustrated embodiment, carrier gas continues to flow at aconstant rate during both phases of each cycle. It will be understood,however, that reactants can be removed by evacuation of the chamberbetween alternating gas pulses. In one arrangement, the preferredreactor incorporates hardware and software to maintain a constantpressure during the pulsed deposition. The disclosures of U.S. Pat. No.4,747,367, issued May 31, 1988 to Posa and U.S. Pat. No. 4,761,269,issued Aug. 2, 1988 to Conger et al., are incorporated herein byreference.

[0147] Following ALD formation of the initial conductive thin film(s),preferably by process(es) similar to that of Table VII and/or TableVIII, conventional deposition processes can form the remainder of thetop electrode. CVD and even PVD can be utilized to deposit an additional100 nm to 500 nm of conductive material. Conventional deposition willnot generally coat the initial thin film(s) with high step coverage, andtherefore will not conform with precision to the underlying textureimposed by the bottom electrode and extended by the highly conformaldielectric and initial conductive thin films. Imperfect step coverage bythe bulk deposition, however, will not result in loss of capacitance,since the initial conductive thin film(s) ensure continuous andconformal coverage of the capacitor dielectric by a portion of the topelectrode.

[0148] Resultant Capacitor Structures

[0149] Referring now to FIG. 7, a bottom electrode 300 is illustratedwith an ultrathin, conformal dielectric layer 302 extending over an HSGlayer 304. In accordance with the needs of DRAM capacitors, thedielectric layer is formed to about the minimal thickness necessary toavoid excessive risk of current leakage and consequent data errors. Inparticular, the dielectric layer 302 coating the bottom electrode 300preferably has a thickness between about 10 Å and 200 Å, and morepreferably between about 25 Å and 100 Å, depending upon the materialused.

[0150] At the same time, high step coverage provided by the methodsdisclosed herein enable formation of the desired thickness uniformlyover all surfaces of the HSG layer, including top, sidewall, reentrantand neck region surfaces. Accordingly, the dielectric layer 302 over theHSG silicon layer 304 has a minimum thickness that is preferably no morethan about 95%, and more preferably no more than about 98% of itsmaximum thickness at any point of the structure and at any point duringthe process.

[0151] Under the preferred conditions, material sufficient for afraction of a monolayer is deposited per cycle, due to the physical sizeof the chemisorbed complex preventing occupation of all available sites,particularly if the adsorbed complex include organic ligands. In exampleof Table IV, ZrO₂ grows at about 0.75 Å/cycle, such that preferablybetween about 30 and 80 cycles, and more preferably between about 30 and50 cycles are performed to produce an adequately thick dielectric layerto avoid operational current leakage and data errors.

[0152] The not shown, the skilled artisan will readily appreciate that atop electrode layer is then formed over the dielectric layer 302 andfabrication completed.

[0153] Referring now to FIG. 8, wherein like reference numerals are usedfor like parts, a similar bottom electrode 300 is shown with a similarlyconformal dielectric layer 302 over an HSG silicon layer 304.Additionally, a barrier layer 306 is formed between the dielectric 302and the HSG silicon surface 304. In accordance with the example ofTables II and III above, for example, a thermally grown silicon nitridelayer serves as the barrier layer 306 under a tantalum oxide dielectric302. Thus, the readily oxidized HSG silicon 304 is somewhat protectedagainst oxidation. Silicon nitride effectively becomes part of thecapacitor dielectric, lowering the effective dielectric constant, butbetter protects the lower electrode 300 from oxidation.

[0154] Referring now to FIG. 9, a bottom electrode 300 is schematicallyshown with an in-progress nanolaminate dielectric 302 conformallyextending over an HSG silicon layer 304. The partially fabricateddielectric stack 302 preferably comprises about 3 Å to 10 Å of a firstdielectric sublayer 302 a (e.g., 5 Å TiO₂); about 3 Å to 10 Å of asecond dielectric sublayer (e.g., 5 Å Ta₂O₅); about 3 Å to 10 Å of thirddielectric sublayer (e.g., 5 Å TiO₂); etc. As will be appreciated,several additional layers of the same or different construction can beadded to complete a leakage-free memory cell capacitor.

[0155] Referring now to FIG. 10, a capacitor bottom electrode 300,including HSG silicon 304, has an ultrathin, high k dielectric 302conforming thereto, as described with respect to FIG. 7. Additionally,FIG. 10 illustrates a top electrode formed over the high k dielectric302. Advantageously, the top electrode includes an initial conductivethin film 308, formed by ALD directly over the high k dielectric. Sincethe conductive thin film 308 is deposited by the ALD process describedwith respect to Table VII and/or Table VIII, the conductive layer 308conformally coats the capacitor dielectric, thus ensuring full topelectrode coverage of the high surface capacitor. At the same time, aremaining portion 310 of the top electrode can be formed by conventionalmeans, such as CVD or PVD, without loss of capacitance.

[0156] In one example, where the capacitor dielectric comprises avolatile material such as Ta₂O₅, the initial thin conductive film 308comprises a thin (e.g., between about 10 nm and 30 nm) barrier layer,exemplified by the TiN formed by the process of Table VII. In this case,the remainder 310 of the top electrode preferably includes about another100 nm of metal nitride to leave an effective thickness for the barrierfunction. The remaining portion 310 of the top electrode preferably alsoincludes a more conductive material, such as an elemental metal,deposited thereover.

[0157] In another example, the initial thin conductive film 308comprises a thin (e.g., between about 10 nm and 30=m) elemental metallayer, exemplified by the W formed by the process of Table VIII. In thiscase, the remainder 310 of the top electrode preferably includes aboutanother 100-500 nm of conductive material and preferably elemental metalto leave an effective thickness for the top electrode.

[0158] Although the foregoing invention has been described in terms ofcertain preferred embodiments, other embodiments will be apparent tothose of ordinary skill in the art. For example, while processes arespecifically provided for particular dielectric materials, the skilledartisan will readily appreciate that ALD methods can be applied toforming capacitors with other materials. Moreover, although illustratedin connection with particular process flows and structures for memorycell capacitors, the skilled artisan will appreciate variations of suchschemes for which the methods disclosed herein will have utility.Additionally, other combinations, omissions, substitutions andmodification will be apparent to the skilled artisan, in view of thedisclosure herein. Accordingly, the present invention is not intended tobe limited by the recitation of the preferred embodiments, but isinstead to be defined by reference to the appended claims.

We claim:
 1. A capacitor structure in an integrated circuit, comprising: a bottom electrode conforming to a macrostructural three-dimensional folding shape and having a textured silicon surface; and an ALD-deposited capacitor dielectric having a dielectric constant greater than about 10 conforming to the textured surface, the dielectric having a maximum thickness of X, wherein X is a single numerical value being less than about 100 Å and at all points over the bottom electrode the capacitor dielectric has a minimum thickness of at least about 0.95 times X, wherein the dielectric comprises a compound including a transition metal.
 2. The structure of claim 1., further comprising a top electrode conforming to the dielectric, the top electrode continuously contacting the dielectric over the entire textured surface.
 3. The structure of claim 2, wherein the top electrode comprises a conductive barrier layer continuously contacting the dielectric over the entire textured surface and a more conductive material formed over the conductive barrier layer.
 4. The structure of claim 2, wherein the top electrode comprises an elemental metal layer continuously contacting the dielectric over the entire textured surface.
 5. The structure of claim 1, wherein the capacitor dielectric comprises a metal oxide.
 6. The structure of claim 7, wherein the dielectric further comprises aluminum oxide.
 7. The structure of claim 5, wherein the metal oxide comprises an oxide of the transition metal.
 8. The structure of claim 7, further comprising a conformal barrier layer formed between the textured silicon layer and the dielectric.
 9. The structure of claim 7, wherein the metal oxide layer comprises an oxide of a Group IV transition metal.
 10. The structure of claim 7, wherein the metal oxide comprises an oxide of a Group V transition metal.
 11. The structure of claim 1, wherein the dielectric comprises a ternary material.
 12. The structure of claim 11, wherein the dielectric comprises a metal, silicon and oxygen.
 13. The structure of claim 1, wherein the maximum thickness X of the capacitor dielectric is between about 25 Å and 100 Å.
 14. The structure of claim 1, wherein at all points over the bottom electrode the capacitor dielectric has a minimum thickness of at least about 0.98 times X. 